? semiconductor components industries, llc, 2000 march, 2000 rev. 4 1 publication order number: mc10h641/d !
the mc10h/100h641 is a single supply, low skew translating 1:9 clock driver. devices in the motorola h600 translator series utilize the 28lead plcc for optimal power pinning, signal flow through and electrical performance. the device features a 24ma ttl output stage, with ac performance specified into a 50pf load capacitance. a latch is provided onchip. when len is low (or left open, in which case it is pulled low by the internal pulldown) the latch is transparent. a high on the enable pin (en ) forces all outputs low. both the len and en pins are positive ecl inputs. the v bb output is provided in case the user wants to drive the device with a singleended input. for singleended use the v bb should be connected to the d input and bypassed with a 0.01 m f capacitor. the 10h version of the h641 is compatible with positive mecl 10h ? logic levels. the 100h version is compatible with positive 100k levels. ? peclttl version of popular eclinps e111 ? low skew ? guaranteed skew spec ? latched input ? differential ecl internal design ? v bb output for singleended use ? single +5v supply ? logic enable ? extra power and ground supplies ? separate ecl and ttl supply pins vbb d d ve len ge en 1 gt q5 vt q4 vt q3 gt gt q6 vt q7 vt q8 gt gt q6 vt q7 vt q8 gt gt q2 vt q1 vt q0 gt 56 7891011 25 24 23 22 21 20 19 26 27 28 2 3 4 18 17 16 15 14 13 12 pinout: 28lead plcc (top view) http://onsemi.com device package shipping ordering information mc10h641fn plcc28 37 units/rail marking diagram a = assembly location wl = wafer lot yy = year ww = work week plcc28 fn suffix case 776 10h641 awlyyww 1 pin names function ttl gnd, ttl v cc ecl gnd, ecl v cc signal input (positive ecl) v bb reference output (positive ecl) signal outputs (ttl) enable input (positive ecl) latch enable input (positive ecl) pins gt, vt ge, ve d, d v bb q0q8 en len mc100h641fn plcc28 37 units/rail
mc10h641, mc100h641 http://onsemi.com 2 ttl outputs pecl input q0 q1 q2 q3 q4 q5 q6 q7 q8 d vbb len dq d en logic diagram dc characteristics (vt = ve = 5.0v 5%) t a = 0 c t a = + 25 c t a = + 85 c symbol characteristic min typ max min typ max min typ max unit condition i ee power supply current pecl 24 30 24 30 24 30 ma i cch ttl 24 30 24 30 24 30 ma i ccl 27 35 27 35 27 35 ma ttl dc characteristics (vt = ve = 5.0v 5%) 0 c 25 c 85 c symbol characteristic min max min max min max unit condition v oh output high voltage 2.5 2.5 2.5 v i oh = 15ma v ol output low voltage 0.5 0.5 0.5 v i ol = 24ma i os output short circuit current 100 225 100 225 100 225 ma v out = 0v 10h pecl dc characteristics 0 c 25 c 85 c symbol characteristic min max min max min max unit condition i ih input high current 225 175 175 m a i il input low current 0.5 0.5 0.5 m a v ih input high voltage 3.83 4.16 3.87 4.19 3.94 4.28 v ve = 5.0v 1 v il input low voltage 3.05 3.52 3.05 3.52 3.05 3.55 v ve = 5.0v 1 v bb output reference voltage 3.62 3.73 3.65 3.75 3.69 3.81 v ve = 5.0v 1 1. pecl v ih , v il , and v bb are referenced to ve and will vary 1:1 with the power supply. the levels shown are for ve = 5.0v.
mc10h641, mc100h641 http://onsemi.com 3 100h pecl dc characteristics 0 c 25 c 85 c symbol characteristic min max min max min max unit condition i inh input high curren 225 175 175 m a i inl input low current 0.5 0.5 0.5 m a v ih input high voltage 3.835 4.120 3.835 4.120 3.835 4.120 v ve = 5.0v 1 v il input low voltage 3.190 3.525 3.190 3.525 3.190 3.525 v ve = 5.0v 1 v bb output reference voltage 3.62 3.74 3.62 3.74 3.62 3.74 v ve = 5.0v 1 1. pecl v ih , v il , and v bb are referenced to ve and will vary 1:1 with the power supply. the levels shown are for ve = 5.0v. ac characteristics (vt = ve = 5.0v 5%) t j = 0 c t j = + 25 c t j = + 85 c symbol characteristic min typ max min typ max min typ max unit condition t plh t phl propagation delay d to q 5.00 5.36 5.50 5.86 6.00 6.36 4.86 5.27 5.36 5.77 5.86 6.27 5.08 5.43 5.58 5.93 6.08 6.43 ns cl = 50 pf 1 t skew device skew parttopart single v cc outputtooutput 1000 750 350 1000 750 350 1000 750 350 ps cl = 50pf 2 cl = 50 pf 3 cl = 50 pf 4 t plh t phl propagation delay len to q 4.9 6.9 4.9 6.9 5.0 7.0 ns cl = 50 pf t plh t phl propagation delay en to q 5.0 7.0 4.9 6.9 5.0 7.0 ns cl = 50 pf t r t f output rise/fall 0.8v to 2.0v 1.7 1.6 1.7 1.6 1.7 1.6 ns cl = 50 pf f max max input frequency 65 65 65 mhz cl = 50 pf 5 t s setup time 0.75 0.50 0.75 0.50 0.75 0.50 ns t h hold time 0.75 0.50 0.75 0.50 0.75 0.50 ns 1. propagation delay measurement guaranteed for junction temperatures. measurements performed at 50mhz input frequency. 2. skew window guaranteed for a single temperature across a v cc = v t = v e of 4.75v to 5.25v (see application note in this datasheet). 3. skew window guaranteed for a single temperature and single v cc = v t = v e 4. outputtooutput skew is specified for identical transitions through the device. 5. frequency at which output levels will meet a 0.8v to 2.0v minimum swing. determining skew for a specific application the h641 has been designed to meet the needs of very low skew clock distribution applications. in order to optimize the device for this application special considerations are necessary in the determining of the parttopart skew specification limits. older standard logic devices are specified with relatively slack limits so that the device can be guaranteed over a wide range of potential environmental conditions. this range of conditions represented all of the potential applications in which the device could be used. the result was a specification limit that in the vast majority of cases was extremely conservative and thus did not allow for an optimum system design. for noncritical skew designs this practice is acceptable, however as the clock speeds of systems increase overly conservative specification limits can kill a design. the following will discuss how users can use the information provided in this data sheet to tailor a parttopart skew specification limit to their application. the skew determination process may appear somewhat tedious and time consuming, however if the utmost in performance is required this procedure is necessary. for applications which do not require this level of skew performance a generic parttopart skew limit of 2.5ns can be used. this limit is good for the entire ambient temperature range, the guaranteed v cc (v t , v e ) range and the guaranteed operating frequency range.
mc10h641, mc100h641 http://onsemi.com 4 temperature dependence a unique characteristic of the h641 data sheet is that the ac parameters are specified for a junction temperature rather than the usual ambient temperature. because very few designs will actually utilize the entire commercial temperature range of a device a tighter propagation delay window can be established given the smaller temperature range. because the junction temperature and not the ambient temperature is what affects the performance of the device the parameter limits are specified for junction temperature. in addition the relationship between the ambient and junction temperature will vary depending on the frequency, load and board environment of the application. since these factors are all under the control of the user it is impossible to provide specification limits for every possible application. therefore a baseline specification was established for specific junction temperatures and the information that follows will allow these to be tailored to specific applications. since the junction temperature of a device is difficult to measure directly, the first requirement is to be able to atranslateo from ambient to junction temperatures. the standard method of doing this is to use the power dissipation of the device and the thermal resistance of the package. for a ttl output device the power dissipation will be a function of the load capacitance and the frequency of the output. the total power dissipation of a device can be described by the following equation: p d (watts) = i cc (no load) * v cc + v s * v cc * f * c l * # outputs where: v s = output voltage swing = 3v f = output frequency c l = load capacitance i cc = i ee + i cch figure 1 plots the i cc versus frequency of the h641 with no load capacitance on the output. using this graph and the information specific to the application a user can determine the power dissipation of the h641. figure 1. i cc versus f (no load) 0 1020304050607080 frequency (mhz) normalized icc 0 1 2 3 4 5 figure 2 illustrates the thermal resistance (in c/w) for the 28lead plcc under various air flow conditions. by reading the thermal resistance from the graph and multiplying by the power dissipation calculated above the junction temperature increase above ambient of the device can be calculated. 0 200 400 600 800 1000 airflow (lfpm) thermal resistance ( 30 40 50 60 70 c/w) figure 2. ? ja versus air flow finally taking this value for junction temperature and applying it to figure 3 allows the user to determine the propagation delay for the device in question. a more common use would be to establish an ambient temperature range for the h641's in the system and utilize the above methodology to determine the potential increased skew of the distribution network. note that for this information if the t pd versus temperature curve were linear the calculations would not be required. if the curve were linear over all temperatures a simple temperature coefficient could be provided. figure 3. t pd versus junction temperature 30 junction temperature ( propagation delay (ns) 5.2 10 10 30 50 70 90 110 130 c) 5.4 5.6 5.8 6.0 6.2 6.4 t phl t plh
mc10h641, mc100h641 http://onsemi.com 5 v cc dependence ttl and cmos devices show a significant propagation delay dependence with v cc . therefore the v cc variation in a system will have a direct impact on the total skew of the clock distribution network. when calculating the skew between two devices on a single board it is very likely an assumption of identical v cc 's can be made. in this case the number provided in the data sheet for parttopart skew would be overly conservative. by using figure 4 the skew given in the data sheet can be reduced to represent a smaller or zero variation in v cc . the delay variation due to the specified v cc variation is 270ps. therefore, the 1ns window on the data sheet can be reduced by 270ps if the devices in question will always experience the same v cc . the distribution of the propagation delay ranges given in the data sheet is actually a composite of three distributions whose means are separated by the fixed difference in propagation delay at the typical, minimum and maximum v cc . figure 4. d t pd versus v cc 4.75 vcc (v) t 140 4.85 4.95 5.05 5.15 5.25 100 60 20 20 60 100 140 t plh t phl d pd (ps) capacitive load dependence as with v cc the propagation delay of a ttl output is intimately tied to variation in the load capacitance. the skew specifications given in the data sheet, of course, assume equal loading on all of the outputs. however situations could arise where this is an impossibility and it may be necessary to estimate the skew added by asymmetric loading. in addition the propagation delay numbers are provided only for 50pf loads, thus necessitating a method of determining the propagation delay for alternative loads. figure 5 shows the relationship between the two propagation delays with respect to the capacitive load on the output. utilizing this graph and the 50pf limits the specification of the h641 can be mapped into a spec for either a different value load or asymmetric loads. figure 5. t pd versus load 0 capacitive load (pf) mormalized propagation delay (ns) 0.75 10 20 30 40 50 60 70 80 90 100 0.80 0.85 0.90 0.95 1.00 1.05 1.10 1.15 t phl t plh measured theoretical rise/fall skew determination the risetofall skew is defined as simply the difference between the t plh and the t phl propagation delays. this skew for the h641 is dependent on the v cc applied to the device. notice from figure 4 the opposite relationship of t pd versus v cc between t plh and t phl . because of this the risetofall skew will vary depending on v cc . since in all likelihood it will be impossible to establish the exact value for v cc , the expected variation range for v cc should be used. if this variation will be the 5% shown in the data sheet the risetofall skew could be established by simply subtracting the fastest t plh from the slowest t phl ; this exercise yields 1.41ns. if a tighter v cc range can be realized figure 4 can be used to establish the risetofall skew. specification limit determination example the situation pictured in figure 6 will be analyzed as an example. the central clock is distributed to two different cards; on one card a single h641 is used to distribute the clock while on the second card two h641's are required to supply the needed clocks. the data sheet as well as the graphical information of this section will be used to calculate the skew between h641a and h641b as well as the skew between all three of the devices. only the t plh will be analyzed, the t phl numbers can be found using the same technique. the following assumptions will be used: all outputs will be loaded with 50pf all outputs will toggle at 30mhz the v cc variation between the two boards is 3% the temperature variation between the three devices is 15 c around an ambient of 45 c. 500lfpm air flow
mc10h641, mc100h641 http://onsemi.com 6 the first task is to calculate the junction temperature for the devices under these conditions. using the power equation yields: p d =i cc (no load) * v cc + v cc * v s * f * c l * # outputs = 4.3 * 48ma * 5v + 5v * 3v * 30mhz * 50pf * 9 = 432mw + 203mw = 635mw using the thermal resistance graph of figure 2 yields a thermal resistance of 41 c/w which yields a junction temperature of 71 c with a range of 56 c to 86 c. using the t pd versus temperature curve of figure 3 yields a propagation delay of 5.42ns and a variation of 0.19ns. since the design will not experience the full 5% v cc variation of the data sheet the 1ns window provided will be unnecessarily conservative. using the curve of figure 4 shows a delay variation due to a 3% v cc variation of 0.075ns. therefore the 1ns window can be reduced to 1ns (0.27ns 0.15ns) = 0.88ns. since h641a and h641b are on the same board we will assume that they will always be at the same v cc ; therefore the propagation delay window will only be 1ns 0.27ns = 0.73ns. putting all of this information together leads to a skew between all devices of 0.19ns + 0.88ns (temperature + supply, and inherent device), while the skew between devices a and b will be only 0.19ns + 0.73ns (temperature + inherent device only). in both cases, the propagation delays will be centered around 5.42ns, resulting in the following t plh windows: t plh = 4.92ns 5.99ns; 1.07ns window (all devices) t plh = 5.00ns 5.92ns; 0.92ns window (devices a & b) of course the outputtooutput skew will be as shown in the data sheet since all outputs are equally loaded. this process may seem cumbersome, however the delay windows, and thus skew, obtained are significantly better than the conservative worst case limits provided at the beginning of this note. for very high performance designs, this extra information and effort can mean the difference between going ahead with prototypes or spending valuable engineering time searching for alternative approaches. q0 q8 ttl ecl h641a q0 q8 ttl ecl h641b q0 q8 ttl ecl h641c card 1 card 2 backplane figure 6. example application
mc10h641, mc100h641 http://onsemi.com 7 package dimensions plcc28 fn suffix plastic plcc package case 77602 issue d notes: 1. datums l, m, and n determined where top of lead shoulder exits plastic body at mold parting line. 2. dimension g1, true position to be measured at datum t, seating plane. 3. dimensions r and u do not include mold flash. allowable mold flash is 0.010 (0.250) per side. 4. dimensioning and tolerancing per ansi y14.5m, 1982. 5. controlling dimension: inch. 6. the package top may be smaller than the package bottom by up to 0.012 (0.300). dimensions r and u are determined at the outermost extremes of the plastic body exclusive of mold flash, tie bar burrs, gate burrs and interlead flash, but including any mismatch between the top and bottom of the plastic body. 7. dimension h does not include dambar protrusion or intrusion. the dambar protrusion(s) shall not cause the h dimension to be greater than 0.037 (0.940). the dambar intrusion(s) shall not cause the h dimension to be smaller than 0.025 (0.635). n m l v w d d y brk 28 1 view s s lm s 0.010 (0.250) n s t s lm m 0.007 (0.180) n s t 0.004 (0.100) g1 g j c z r e a seating plane s lm m 0.007 (0.180) n s t t b s lm s 0.010 (0.250) n s t s lm m 0.007 (0.180) n s t u s lm m 0.007 (0.180) n s t z g1 x view dd s lm m 0.007 (0.180) n s t k1 view s h k f s lm m 0.007 (0.180) n s t dim min max min max millimeters inches a 0.485 0.495 12.32 12.57 b 0.485 0.495 12.32 12.57 c 0.165 0.180 4.20 4.57 e 0.090 0.110 2.29 2.79 f 0.013 0.019 0.33 0.48 g 0.050 bsc 1.27 bsc h 0.026 0.032 0.66 0.81 j 0.020 0.51 k 0.025 0.64 r 0.450 0.456 11.43 11.58 u 0.450 0.456 11.43 11.58 v 0.042 0.048 1.07 1.21 w 0.042 0.048 1.07 1.21 x 0.042 0.056 1.07 1.42 y 0.020 0.50 z 2 10 2 10 g1 0.410 0.430 10.42 10.92 k1 0.040 1.02
mc10h641, mc100h641 http://onsemi.com 8 on semiconductor and are trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scill c data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent r ights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into t he body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. publication ordering information asia/pacific : ldc for on semiconductor asia support phone : 3036752121 (tuefri 9:00am to 1:00pm, hong kong time) toll free from hong kong 80044223781 email : onlitasia@hibbertco.com japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1418549 phone : 81357402745 email : r14525@onsemi.com fax response line : 3036752167 8003443810 toll free usa/canada on semiconductor website: http://onsemi.com for additional information, please contact your local sales representative. mc10h641/d north america literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com n. american technical support : 8002829855 toll free usa/canada europe: ldc for on semiconductor european support german phone: (+1) 3033087140 (mf 2:30pm to 5:00pm munich time) email: onlitgerman@hibbertco.com french phone: (+1) 3033087141 (mf 2:30pm to 5:00pm toulouse time) email: onlitfrench@hibbertco.com english phone: (+1) 3033087142 (mf 1:30pm to 5:00pm uk time) email: onlit@hibbertco.com
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